In the fabrication of ultra-large-scale integration (ULSI) circuits, vertical stacking, or integration, of a plurality of metal wiring circuits to form multilevel interconnection has become an efficient way to increase circuit performance and increase the functional complexity of the circuits. One drawback of multilevel interconnection is the loss of topological planarity resulting from various photolithographic and etching processes. To alleviate these problems, the wafer is planarized at various stages in the fabrication process to minimize non-planar topography and thus its adverse effects. Such planarization is typically implemented in the dielectric layers.
More recently, chemical-mechanical polishing (CMP) processes have become very well received to planarize the wafer surface in preparation for further device fabrication. The CMP process mainly involves holding a semiconductor wafer against a rotating polishing pad surface wetted by a polishing slurry, which typically comprises an acidic or basic etching solution in combination with alumina or silica particles. On the one hand, the liquid portion of the slurry chemically removes, loosens, or modifies the composition of the material on the wafer which is to be removed. On the other hand, the particle portion of the slurry, in combination of the rotating polishing pad, physically removes the chemical modified material from the wafer. Thus, the name chemical-mechanical polishing was obtained.
One of the main applications of the CMP process is to planarize the intermetal dielectric layer (IMD), or the so-called sacrificial layer, which is typically deposited via a chemical vapor deposition technique on a metal wiring layer to facilitate the fabrication of the next metal wiring layer. The intermetal dielectric layer typically comprises silicon dioxide or silicon nitride to provide shallow trench isolation, interlayer dielectrics, intermetal (i.e., between successive metal wiring layers) dielectrics and other insulation layers.
Due to the topography of the device (i.e, the wiring layer) upon which the sacrificial layer is to be deposited, typically via a chemical vapor deposition (CVD) technique, the thickness of the sacrificial layer has to be very high in order to achieve a satisfactorily planarized surface. On the other hand, the chemical portion (etching) of the CMP process often causes the recessed portions of the IMD layer to be etched (the dishing effect) before the mechanical portion of the CMP process is acting thereupon. This can cause the deviations of the final polished surface of the IMD layer to be even more significant than before polishing. As a result, a CVD composition with low CMP removal rate must be employed to avoid such dishing effect. The use of a low CMP removal rate CVD composition can substantially slow down the CMP processing cost. Thus, it is highly desirable to develop a process which could reduce the required sacrificial layer thickness and the polishing time so as to reduce the CMP/CVD processing time, reduce the overall fabrication cost, and improve the uniformity of the polished device.
U.S. Pat. No. 4,671,970, the content thereof is incorporated herein by reference, discloses a process for creating dielectric material filled trenches of diverse widths between active regions of a semiconductor which comprises the steps of forming a first conformal layer of oxidation barrier over the trenches and the active regions; forming a second conformal layer over the oxidation barrier which comprises a material characterized by its ability to withstand etchants and its subsequent convertability to a dielectric; forming a third conformal layer of a dielectric material; selectively removing dielectric material from the active regions, the narrow width trenches, and the perimeter regions of the wide width trenches; converting the material of the second conformal layer to a dielectric; filling the regions of selectively removed dielectric material with a further dielectric material to above the level above the planar of the active regions; and planarizating the substrate to the level of the active regions.
U.S. Pat. No. 5,395,801, the content thereof is incorporated herein by reference, discloses a semiconductor processing method of providing and planarizing an insulting layer on a semiconductor wafer comprising the steps of: (1) providing a conformal layer of insulating material over a semiconductor wafer; (2) providing a blanketing chemical-mechanical polishing protective layer over the conformal layer; and (3) chemical-mechanical polishing through the outermost surface of the blanketing layer and then through conformal layer in a single chemical-mechanical polishing step using a single chemical-mechanical polishing slurry. The protective layer provides the function of restricting material removal from low topographical areas during such chemical-mechanical polishing. Typically, .alpha.-silicon, carbon, boron nitride, undoped SiO.sub.2, etc. have been used or suggested for use as the protective material. One of the drawbacks of this process is that, since the material for the protective layer is quite different from that for the main sacrificial layer, the CVD process must be switched to a very different condition. This greatly complicates the fabrication process, introduces contamination concerns, and significantly increases the fabrication cost; it can also raise compatibility problems and may be difficult to be integrated into the standard IC process.
U.S. Pat. No. 5,532,191, the content thereof is incorporated herein by reference, discloses a method for planarization an insulating layer comprising the steps of: (1) forming an insulating film on a substrate by chemical vapor deposition using an organic silicon compound, coating a solution of an insulating substance on the substrate and coating a solution of a precursor of an insulating substance on the substrate; (2) forming a protective film having a chemical mechanical polishing etching speed slower than that of the insulating film by depositing silicon oxide and silicon oxynitride via chemical vapor deposition using an inorganic silicon compound as a raw material; and (3) etching back the insulating film by chemical mechanical polishing using the protective film as an etching stop.
The processes disclosed in the above mentioned references either increased the complexity of the CMP process or did not significant reduce the required CMP processing time. Thus, continued efforts are required to provide possible answers to the problems herein described. These problems are becoming more profound and pressing, as the IC processes are now moving into 0.25 .mu.m or finer.